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| cywusb6935 wirelessusb? lr 2.4 ghz dsss radio soc cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 38-16008 rev. *g revised october 05, 2010 features 2.4-ghz radio transceiver operates in the unlicensed industrial, scientific, and medical (ism) band (2.4 ghz to 2.483 ghz) receive sensitivity: ?95 dbm up to 0 dbm output power range of up to 50 meters or more data throughput of up to 62.5 kbits/sec highly integrated low cost, minimal number of external compo- nents required dual direct sequence spread spectrum (dsss) reconfigurable baseband correlators spi microcontroller interface (up to 2 mhz data rate) 13-mhz input clock operation low standby current < 1 a integrated 30-bit manufacturing id operating voltage from 2.7 v to 3.6 v operating temperature from ?40 c to 85 c offered in a small footprint 48 qfn functional description the cywusb6935 transceiver is a single-chip 2.4 ghz dsss gaussian frequency shift keying (gfsk) baseband modem radio that connects directly to a microcontroller via a simple serial peripheral interface. the cywusb6935 is offered in an industrial temperature range 48-pin qfn and a commercial temperature range 48-pin qfn. logic block diagram ? cywusb6935 digital synthesizer gfsk demodulator gfsk modulator irq ss sck miso mosi reset pd dio diov a l rfout rfin x13in x13 x13out serdes b serdes a dsss baseband a dsss baseband b [+] feedback not recommended for new designs
cywusb6935 document number : 38-16008 rev. *g page 2 of 36 contents applications ...................................................................... 3 applications support ................................................... 3 functional overview ........................................................ 3 2.4 ghz radio ............................................................. 3 gfsk modem ..... ................................................ ......... 3 dual dsss baseband ............ ............................ ......... 3 serializer/deserializer (serd es) ............................... 4 application interfaces .................................................. 4 clocking and power management .............................. 4 receive signal strength indicator (rssi) ................... 4 application interfaces ...................................................... 4 spi interface ................................................................ 4 dio interface ............................................................... 6 interrupts ..................................................................... 6 application examples ...................................................... 7 register descriptions ...................................................... 8 absolute maximum ratings .......................................... 25 operating conditions ..................................................... 25 dc characteristics (over the operating range) ............ 25 ac characteristics ......................................................... 26 radio parameters ..................................................... 28 power management timing ...................................... 29 typical operating characteristics ............................. 30 ordering information ...................................................... 32 ordering code definition .... ....................................... 32 package diagram ............................................................ 33 acronyms ........................................................................ 34 document conventions ................................................. 34 document history page ................................................. 35 sales, solutions, and legal information ...................... 36 worldwide sales and design s upport ......... .............. 36 products .................................................................... 36 psoc solutions ......................................................... 36 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 3 of 36 applications building/home automation ? climate control ? lighting control ? smart appliances ? on-site paging systems ? alarm and security industrial control ? inventory management ? factory automation ? data acquisition automatic meter reading (amr) transportation ? diagnostics ? remote keyless entry consumer / pc ? locator alarms ? presenter tools ? remote controls ? toys applications support the cywusb6935 is supported by both the cy3632 wirelessusb development kit and the cy3635 wirelessusb n:1 development kit. the cy3635 development kit provides all of the materials and documents needed to cut the cord on multi- point to point and point-to-point low bandwidth, high node density applications including four small form-factor sensor boards and a hub board that connects to wirelessusb lr rf module boards, a software application that graphically demonstrates the multipoint to point protocol, comprehensive wirelessusb protocol code examples and all of the associated schematics, gerber files and bill of materials. the wirelessusb n:1 devel- opment kit is also supported by the wirelessusb listener tool. functional overview the cywusb6935 provides a complete spi-to-antenna radio modem. the cywusb6935 is designed to implement wireless devices operating in the worldwide 2.4-ghz industrial, scientific, and medical (ism) frequency band (2.400 ghz?2.4835 ghz). it is intended for systems compli ant with world-wi de regulations covered by etsi en 301 489-1 v1.4.1, etsi en 300 328-1 v1.3.1 (european countries); fcc cfr 47 part 15 (usa and industry canada) and arib std-t66 (japan). the cywusb6935 contains a 2.4-ghz radio transceiver, a gfsk modem, and a dual dsss reconfigurable baseband. the radio and baseband are both code- and frequency-agile. forty-nine spreading codes selected for optimal performance (gold codes) are supported ac ross 78 1-mhz channels yielding a theoretical spectral capacity of 3822 channels. the cywusb6935 supports a range of up to 50 meters or more. 2.4 ghz radio the receiver and transmitter are a single-conversion, low-inter- mediate frequency (low-if) archit ecture with fully integrated if channel matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides an output power control range of 30 db in seven steps. both the receiver and transmitter integrated voltage controlled oscillator (vco) and synthesizer have the agility to cover the complete 2.4-ghz gfsk radio transmitter ism band. the synthesizer provides the frequen cy-hopping local oscillator for the transmitter and receiver. the vco loop filter is also integrated on-chip. gfsk modem the transmitter uses a dsp-bas ed vector modulator to convert the 1-mhz chips to an accurate gfsk carrier. the receiver uses a fully integrated frequency modulator (fm) detector with automatic data slicer to demodulate the gfsk signal. dual dsss baseband data is converted to dsss ch ips by a digital spreader. de-spreading is performed by an oversampled correlator. the dsss baseband cancels spurious noise and assembles properly correlated data bytes. the dsss baseband has three operating modes: 64-chips/bit single channel, 32-chips/bit single channel, and 32-chips/bit single channel dual data rate (ddr). 64 chips/bit single channel the baseband supports a single da ta stream operating at 15.625 kbits/sec. the advantage of selecting this mode is its ability to tolerate a noisy environment. this is because the 15.625 kbits/sec data stream utilizes the longest pn code resulting in the highest probability for recovering packets over the air. this mode can also be selected for syst ems requiring data transmis- sions over longer ranges. 32 chips/bit single channel the baseband supports a single data stream operating at 31.25 kbits/sec. 32 chips/bit single channel dual data rate (ddr) the baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/sec. table 1. internal pa output power step table pa setting typical output power (dbm) 70 6 ?2.4 5 ?5.6 4 ?9.7 3 ?16.4 2 ?20.8 1 ?24.8 0 ?29.0 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 4 of 36 serializer/deserializer (serdes) cywusb6935 provides a data serializer/deserializer (serdes), which provides byte-level framing of transmit and receive data. bytes for transmission are loaded into the serdes and receive bytes are read from the serdes via the spi interface. the serdes provides double buffering of transmit and receive data. while one byte is being transmitted by the radio the next byte can be written to the serdes data register insuring there are no breaks in transmitted data. after a receive byte has been received it is loaded into the serdes data register and can be read at any time until the next byte is received, at which time the old contents of the serdes data register will be overwritten. application interfaces cywusb6935 has a fully synchronous spi slave interface for connectivity to the application mcu. configuration and byte-oriented data transfer can be performed over this interface. an interrupt is provided to trigger real time events. an optional serdes bypass mode (dio) is provided for appli- cations that require a synchronous serial bit-oriented data path. this interface is for data only. clocking and power management a 13-mhz crystal is directly connected to x13in and x13 without the need for external capacitors. the cywusb6935 has a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. below are the requirements for the crystal to be directly connected to x13in and x13: nominal frequency: 13 mhz operating mode: fundamental mode resonance mode: parallel resonant frequency stability: 30 ppm series resistance: < 100 ohms load capacitance: 10 pf drive level: 10 w to 100 w the radio frequency (rf) circuitry has on-chip decoupling capac- itors. the cywusb6935 is powered from a 2.7-v to 3.6-v dc supply. the cywusb6935 can be shut down to a fully static state using the pd pin. receive signal strength indicator (rssi) the rssi register (reg 0x22) returns the relative signal strength of the on-channel signal power and can be used to: 1. determine the connection quality 2. determine the value of the noise floor 3. check for a quiet channel before transmitting. the internal rssi voltage is sampled through a 5-bit analog-to-digital converter (adc). a state machine controls the conversion process. under normal conditions, the rssi state machine initiates a conversion when an on-channel carrier is detected and remains above the noise floor for over 50 s. the conversion produces a 5-bit value in the rssi register (reg 0x22, bits 4:0) along with a valid bit, rssi register (reg 0x22, bit 5). the state machine then remains in halt mode and does not reset for a new conversion until the receive mode is toggled off and on. after a connection has been established, the rssi register can be read to determine the relative connection quality of the channel. a rssi register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. to check for a quiet channel be fore transmitting, first set up receive mode properly and read t he rssi register (reg 0x22). if the valid bit is zero, then force the carrier detect register (reg 0x2f, bit 7=1) to initiate an a dc conversion. then, wait greater than 50 s and read the rssi register again. next, clear the carrier detect register (reg 0x2f, bit 7=0) and turn the receiver off. measuring the noise floor of a quiet channel is inherently a 'noisy' process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. a rssi register value of 0-10 indicates a channel that is relatively quiet. a rssi register value greater than 10 indicates the channel is probably being used. a rssi register value greater than 28 indicates the presence of a strong signal. application interfaces spi interface the cywusb6935 has a four-wire spi communication interface between an application mcu and one or more slave devices. the spi interface supports sing le-byte and multi-byte serial transfers. the four-wire spi co mmunications interface consists of master out-slave in (mosi) , master in-slave out (miso), serial clock (sck), and slave select (ss ). the spi receives sck from an application mcu on the sck pin. data from the application mcu is shifted in on the mosi pin. data to the application mcu is sh ifted out on the miso pin. the active-low slave select (ss) pin must be asserted to initiate a spi transfer. the application mcu can initiate a spi data transfer via a multi-byte transaction. the first byte is the command/address byte, and the following bytes are the data bytes as shown in figure 2 through figure 3 . the ss signal should not be deasserted between bytes. the spi communications interface is as follows: command direction (bit 7) = ?0? enables spi read transaction. a ?1? enables spi write transactions. command increment (bit 6) = ?1? enables spi auto address increment. when set, the address field automatically incre- ments at the end of each data byte in a burst access, otherwise the same address is accessed. six bits of address. eight bits of data. the spi communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. a burst transaction is terminated by deasserting the slave select (ss = 1). for burst read transactions, the application mcu must abide by the timing shown in figure 11 . the spi communications interface single read and burst read sequences are shown in figure 1 and figure 2 , respectively. the spi communications interfac e single write and burst write sequences are shown in figure 3 and figure 4 , respectively. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 5 of 36 table 2. spi transaction format byte 1 byte 1+n bit # 7 6 [5:0] [7:0] bit name dir inc address data figure 1. spi single read sequence figure 2. spi burst read sequence figure 3. spi single write sequence figure 4. spi burst write sequence ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data to mcu addr cm d 00 ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data to mcu 1 data to mcu 1+n addr cmd dir inc 01 ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data from mcu addr cmd 10 ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data from mcu 1 data from mcu 1+n addr cmd dir inc 11 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 6 of 36 dio interface the dio communications interface is an optional serdes bypass data-only transfer interface. in receive mode, dio and dioval are valid after the falli ng edge of irq, which clocks the data as shown in figure 5 . in transmit mode, dio and dioval are sampled on the falling edge of the irq, which clocks the data as shown in figure 6 . the application mcu samples the dio and dioval on the rising edge of irq. interrupts the cywusb6935 features three sets of interrupts: transmit, received, and a wake interrupt. these interrupts all share a single pin (irq), but can be independently enabled/disabled. in transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. however, the contents of the enable registers are preserved when switching between transmit and receive modes. interrupts are enabled and the status read through 6 registers: receive interrupt enable (reg 0x07), receive interrupt status (reg 0x08), transmit interrupt enable (reg 0x0d), transmit interrupt status (reg 0x0e), wake enable (reg 0x1c), wake status (reg 0x1d). if more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. it is therefore possible to use the devices without making use of the irq pin at all. firmware can poll the interrupt st atus register(s) to wait for an event, rather than using the irq pin. the polarity of all interrupts can be set by writing to the configu- ration register (reg 0x05), and it is possible to configure the irq pin to be open drain (if active low) or open source (if active high). wake interrupt when the pd pin is low, the oscillator is stopped. after pd is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the spi interface. the wake interrupt indicates that the oscillator has started, and that the device is ready to receive spi transfers. the wake interrupt is enabled by setting bit 0 of the wake enable register (reg 0x1c, bit 0=1). whether or not a wake interrupt is pending is indicated by the state of bit 0 of the wake status register (reg 0x1d, bit 0). reading the wake status register (reg 0x1d) clears the interrupt. transmit interrupts four interrupts are provided to flag the occurrence of transmit events. the interrupts are enabled by writing to the transmit interrupt enable register (reg 0x0d), and their status may be determined by reading the transmit interrupt status register (reg 0x0e). if more than 1 interrupt is enabled, it is necessary to read the transmit interrupt status register (reg 0x0e) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in section . receive interrupts eight interrupts are provided to flag the occurrence of receive events, four each for serdes a and b. in 64 chips/bit and 32 chips/bit ddr modes, only the serdes a interrupts are available, and the serdes b interrupts will never trigger, even if enabled. the interrupts are enabled by writing to the receive interrupt enable register (reg 0x07), and their status may be determined by reading the receive interrupt status register (reg 0x08). if more than one interrupt is enabled, it is necessary to read the receive interrupt status register (reg 0x08) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in section . figure 5. dio receive sequence figure 6. dio transmit sequence dioval dio irq d7d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1d0 data to mcu v7v6v5 v4 v3v2 v... v14 v13 v12 v11 v10 v9v8 v1v0 dioval dio irq d7d6 d5 d4 d3d2 d... d14 d13 d12 d11 d10 d9d8 d1 d0 data from mcu v7v6v5v4v3v2 v... v14 v13 v12 v11 v10 v9v8 v1v0 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 7 of 36 application examples figure 7 shows a block diagram example of a typical battery powered device using the cywusb6935 chip. figure 8 shows an application example of a wirelessusb lr alarm syst em where a single hub node is connected to an alarm panel. the hub node wirelessly receives information from multip le sensor nodes in order to control the alarm panel. figure 7. cywusb6935 battery powered device figure 8. wirelessusb lr alarm system wirelessusb lr psoc ? 8-bit mcu irq spi 4 pd reset vcc vcc ldo/ dc2dc battery + - 0.1 f 13mhz cr y s t al 3.3 v rfout 3.3 nh rfin 2.0 pf pcb tr ace antenna 27 pf application hardware 1.2 pf 2.2 nh 2.0 pf alarm panel wirelessusb lr + psoc wirelessusb lr ? r s 2 3 2 psoc + smoke detector wirelessusb lr psoc + motion detector wirelessusb lr psoc + door sensor wirelessusb lr psoc + keypad [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 8 of 36 register descriptions ta b l e 3 displays the list of registers inside the cywusb6935 that ar e addressable through the spi interface. all registers are read and writable, except where noted. note 1. all registers are accessed little endian. table 3. cywusb6935 register map [1] register name mnemonic cywusb6935 address page default access revision id reg_id 0x00 8 0x07 ro control reg_control 0x03 9 0x00 rw data rate reg_data_rate 0x04 10 0x00 rw configuration reg_config 0x05 11 0x01 rw serdes control reg_serdes_ctl 0x06 11 0x03 rw receive serdes interrupt enable reg_rx_int_en 0x07 12 0x00 rw receive serdes interrupt status reg_rx_int_stat 0x08 13 0x00 ro receive serdes data a reg_rx_data_a 0x09 14 0x00 ro receive serdes valid a reg_rx_valid_a 0x0a 14 0x00 ro receive serdes data b reg_rx_data_b 0x0b 14 0x00 ro receive serdes valid b reg_rx_valid_b 0x0c 14 0x00 ro transmit serdes interrupt enable reg_tx_int_en 0x0d 15 0x00 rw transmit serdes interrupt status reg_tx_int_stat 0x0e 16 0x00 ro transmit serdes data reg_tx_data 0x0f 17 0x00 rw transmit serdes valid reg_tx_valid 0x10 17 0x00 rw pn code reg_pn_code 0x18?0x11 17 0x1e8b6a3de0e9b222 rw threshold low reg_threshold_l 0x19 18 0x08 rw threshold high reg_threshold_h 0x1a 18 0x38 rw wake enable reg_wake_en 0x1c 18 0x00 rw wake status reg_wake_stat 0x1d 19 0x01 ro analog control reg_analog_ctl 0x20 19 0x04 rw channel reg_channel 0x21 19 0x00 rw receive signal strength indicator reg_rssi 0x22 20 0x00 ro pa bias reg_pa 0x23 20 0x00 rw crystal adjust reg_crystal_adj 0x24 20 0x00 rw vco calibration reg_vco_cal 0x26 21 0x00 rw reg power control reg_pwr_ctl 0x2e 21 0x00 rw carrier detect reg_carrier_detect 0x2f 21 0x00 rw clock manual reg_clock_manual 0x32 21 0x00 rw clock enable reg_clock_enable 0x33 22 0x00 rw synthesizer lock count reg_syn_lock_cnt 0x38 22 0x64 rw manufacturing id reg_mid 0x3c?0x3f 22 ? ro [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 9 of 36 table 4. revision id register addr: 0x00 reg_id default: 0x07 76543210 silicon id product id bit name description 7:4 silicon id these are the silicon id revision bits. 0000 = rev a, 0001 = rev b, etc. these bits are read-only. 3:0 product id these are the product id revision bits. fixed at value 0111. these bits are read-only. table 5. control addr: 0x03 reg_control default: 0x00 76543210 rx enable tx enable pn code select bypass internal syn lock signal auto internal pa disable internal pa enable reserved reserved bit name description 7 rx enable the receive enable bit is used to place the ic in receive mode. 1 = receive enabled 0 = receive disabled 6 tx enable the transmit enable bit is used to place the ic in transmit mode. 1 = transmit enabled 0 = transmit disabled 5 pn code select the pseudo-noise code select bit selects between the upper or lower half of the 64 chips/bit pn code. 1 = 32 most significant bits of pn code are used 0 = 32 least significant bits of pn code are used this bit applies only when the code width bit is set to 32 chips/bit pn codes (reg 0x04, bit 2=1). 4 bypass internal syn lock signal this bit controls whether the state machine waits for the internal syn lock signal before waiting for the amount of time specified in the syn lock count register (reg 0x38), in units of 2 s. if the internal syn lock signal is used then set syn lock count to 25 to provide addit ional assurance that the synthesizer has settled. 1 = bypass the internal syn lock signal and wait the am ount of time in syn lock count register (reg 0x38) 0 = wait for the syn lock signal and then wait the am ount of time specified in syn lock count register (reg 0x38) it is recommended that the application mcu sets this bit to 1 in order to guarantee a consistent settle time for the synthesizer. 3 auto internal pa disable the auto internal pa disable bit is used to determine the method of controlling the internal power amplifier. the two options are automatic control by the baseband or by firmware through register writes. for external pa usage, please see the description of the reg_analog_ctl register (reg 0x20). 1 = register controlled internal pa enable 0 = auto controlled internal pa enable when this bit is set to 1, the enabled state of the internal pa is directly controlled by bit internal pa enable (reg 0x03, bit 2). it is recommended that this bit is set to 0, leaving the pa control to the baseband. 2 internal pa enable the internal pa enable bit is used to enable or disable the internal power amplifier. 1 = internal power amplifier enabled 0 = internal power amplifier disabled this bit only applies when the auto internal pa disable bi t is selected (reg 0x03, bit 3=1), otherwise this bit is don?t care. 1 reserved this bit is reserved and should be written with a zero. 0 reserved this bit is reserved and should be written with a zero. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 10 of 36 note 2. the following reg 0x04, bits 2:0 values are not valid: ? 001?not valid ? 010?not valid ? 011?not valid ? 111?not valid table 6. data rate addr: 0x04 reg_data_rate default: 0x00 76543210 reserved code width data rate sample rate bit name description 7:3 reserved these bits are reserved an d should be written with zeroes. 2 [2] code width the code width bit is used to select between 32 chips/bit and 64 chips/bit pn codes. 1 = 32 chips/bit pn codes 0 = 64 chips/bit pn codes the number of chips/bit used impacts a number of fact ors such as data throughput, range and robustness to interference. by choosing a 32 chips/bit pn-code, th e data throughput can be doubled or even quadrupled (when double data rate is set). a 64 chips/bit pn code offers improved range over its 32 chips/bit counterpart as well as more robustness to interference. by selecting to use a 32 chips/bit pn code a number of other register bits are impacted and need to be addressed. these are pn code select (reg 0x03, bit 5), data rate (reg 0x04, bit 1), and sample rate (reg 0x04, bit 0). 1 [2] data rate the data rate bit allows the user to select double data rate mode of operation which delivers a raw data rate of 62.5kbits/sec. 1 = double data rate - 2 bits per pn code (no odd bit transmissions) 0 = normal data rate - 1 bit per pn code this bit is applicable only when using 32 chips/bit pn co des which can be selected by setting the code width bit (reg 0x04, bit 2=1). when using double data rate, the ra w data throughput is 62.5 kbits/sec because every 32 chips/bit pn code is interpreted as 2 bits of data. w hen using this mode a single 64 chips/bit pn code is placed in the pn code register. this 64 chips/bit pn code is then split into two and used by the baseband to offer the double data rate capability. when using normal data rate, the raw data throughput is 32 kb its/sec. additionally, normal data rate enables the user to potentially correlate data using two differing 32 chips/bit pn codes. 0 [2] sample rate the sample rate bit allows the use of the 12x sampling when using 32 chips/bit pn codes and normal data rate. 1 = 12x oversampling 0 = 6x oversampling using 12x oversampling improves the correlators receive se nsitivity. when using 64 chips/bit pn codes or double data rate this bit is don?t care. the only time when 12x oversampling can be selected is when a 32 chips/bit pn code is being used with normal data rate. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 11 of 36 table 7. configuration addr: 0x05 reg_config default: 0x01 76543210 reserved irq pin select bit name description 7:2 reserved these bits are reserved and should be written with zeroes. 1:0 irq pin select the interrupt request pin select bits are used to determine the drive method of the irq pin. 11 = open source (irq asserted = 1, irq deasserted = hi-z) 10 = open drain (irq asserted = 0, irq deasserted = hi-z) 01 = cmos (irq asserted = 1, irq deasserted = 0) 00 = cmos inverted (irq asserted = 0, irq deasserted = 1) table 8. serdes control addr: 0x06 reg_serdes_ctl default: 0x03 76543210 reserved serdes enable eof length bit name description 7:4 reserved these bits are reserved and should be written with zeroes. 3 serdes enable the serdes enable bit is used to switch between bit-serial mode and serdes mode. 1 = serdes enabled 0 = serdes disabled, bit-serial mode enabled when the serdes is enabled data can be written to and read from the ic one byte at a time, through the use of the serdes data registers. the bit-serial mode r equires bits to be written one bit at a time through the use of the dio/dioval pins, refer to section 3.2. it is recommended that serdes mode be used to avoid the need to manage the timing required by the bit-serial mode. 2:0 eof length the end of frame length bits are used to set the number of sequential bit times for an inter-frame gap without valid data before an eof event will be generat ed. when in receive mode and a valid bit has been received the eof event can then be identified by the number of bit times that expire without correlating any new data. the eof event causes data to be moved to the prope r serdes data register and can also be used to generate interrupts. if 0 is the eof length, an eof condition will occur at the first invalid bit after a valid reception. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 12 of 36 table 9. receive serdes interrupt enable addr: 0x07 reg_rx_int_en default: 0x00 76543210 underflow b overflow b eof b full b underflow a overflow a eof a full a bit name description 7 underflow b the underflow b bit is used to enable the interr upt associated with an underflow condition with the receive serdes data b register (reg 0x0b) 1 = underflow b interrupt enabled for receive serdes data b 0 = underflow b interrupt disabled for receive serdes data b an underflow condition occurs when attempting to read the receive serdes data b register (reg 0x0b) when it is empty. 6 overflow b the overflow b bit is used to enable the interrupt associated with an overflow condition with the receive serdes data b register (reg 0x0b) 1 = overflow b interrupt enabled for receive serdes data b 0 = overflow b interrupt disabled for receive serdes data b an overflow condition occurs when new received data is written into the receive serdes data b register (reg 0x0b) before the prior data is read out. 5 eof b the end of frame b bit is used to enable the interr upt associated with the channel b receiver eof condition. 1 = eof b interrupt enabled for channel b receiver 0 = eof b interrupt disabled for channel b receiver the eof irq asserts during an end of frame condition. end of frame conditions occur after at least one bit has been detected, and then the number of invalid bits in the frame exceeds the number in the eof length field. if 0 is the eof length, and eof condition will occur at the first invalid bit after a valid reception. this irq is cleared by reading the receive status register 4 full b the full b bit is used to enable the interrupt associ ated with the receive serdes data b register (reg 0x0b) having data placed in it. 1 = full b interrupt enabled for receive serdes data b 0 = full b interrupt disabled for receive serdes data b a full b condition occurs when data is transferred from the channel b receiver into the receive serdes data b register (reg 0x0b). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. 3 underflow a the underflow a bit is used to enable the interr upt associated with an underflow condition with the receive serdes data a register (reg 0x09) 1 = underflow a interrupt enabled for receive serdes data a 0 = underflow a interrupt disabled for receive serdes data a an underflow condition occurs when attempting to read the receive serdes data a register (reg 0x09) when it is empty. 2 overflow a the overflow a bit is used to enable the interrupt associated with an overflow condition with the receive serdes data a register (0x09) 1 = overflow a interrupt enabled for receive serdes data a 0 = overflow a interrupt disabled for receive serdes data a an overflow condition occurs when new receive data is written into the receive serdes data a register (reg 0x09) before the prior data is read out. 1 eof a the end of frame a bit is used to enable the interrupt associated with an end of frame condition with the channel a receiver. 1 = eof a interrupt enabled for channel a receiver 0 = eof a interrupt disabled for channel a receiver the eof irq asserts during an end of frame condition. end of frame conditions occur after at least one bit has been detected, and then the number of invalid bits in a frame exceeds the number in the eof length field. if 0 is the eof length, an eof condition will occur at the first invalid bit after a valid reception. this irq is cleared by reading the receive status register. 0 full a the full a bit is used to enable the interrupt associ ated with the receive serdes data a register (0x09) having data written into it. 1 = full a interrupt enabled for receive serdes data a 0 = full a interrupt disabled for receive serdes data a a full a condition occurs when data is transferred from the channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 13 of 36 note 3. all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imp lemented without enabling irqs. the status bits are affected by tx enable and rx enable (reg 0x03, bits 7:6) . for example, the receive status will read 0 if the ic is not in receive mode. these registers are read-only. table 10. receive serdes interrupt status [3] addr: 0x08 reg_rx_int_stat default: 0x00 76543210 valid b flow violation b eof b full b va lid a flow violation a eof a full a bit name description 7 valid b the valid b bit is true when all the bits in the receive serdes data b register (reg 0x0b) are valid. 1 = all bits are valid for receive serdes data b 0 = not all bits are valid for receive serdes data b when data is written into the receive serdes data b register (reg 0x0b) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 6flow violation b the flow violation b bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data b register (reg 0x0b). 1 = overflow/underflow interrupt pending for receive serdes data b 0 = no overflow/underflow interrupt pending for receive serdes data b overflow conditions occur when the radio loads new data into the receive serdes data b register (reg 0x0b) before the prior data has been read. underflow conditions occur when trying to read the receive serdes data b register (reg 0x0b) when the register is empty. this bit is cleared by reading the receive interrupt status register (reg 0x08) 5 eof b the end of frame b bit is used to signal whether an eof event has occurred on the channel b receive. 1 = eof interrupt pending for channel b 0 = no eof interrupt pending for channel b an eof condition occurs for the channel b receiver when receive has begun and then the number of bit times specified in the serdes control register (reg 0x06) elapse without any valid bits being received. this bit is cleared by reading the receive interrupt status register (reg 0x08) 4 full b the full b bit is used to signal when the receive serdes data b register (reg 0x0b) is filled with data. 1 = receive serdes data b full interrupt pending 0 = no receive serdes data b full interrupt pending a full b condition occurs when data is transferred from the channel b receiver into the receive serdes data b register (reg 0x0b). this could occur when a complete by te is received or when an eof event occurs whether or not a complete byte has been received. 3 valid a the valid a bit is true when all of the bits in the receive serdes data a register (reg 0x09) are valid. 1 = all bits are valid for receive serdes data a 0 = not all bits are valid for receive serdes data a when data is written into the receive serdes data a register (reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 2flow violation a the flow violation a bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data a register (reg 0x09). 1 = overflow/underflow interrupt pending for receive serdes data a 0 = no overflow/underflow interrupt pending for receive serdes data a overflow conditions occur when the radio loads new data into the receive serdes data a register (reg 0x09) before the prior data has been read. underflow conditions occur when trying to read the receive serdes data a register (reg 0x09) when the register is empty. this bit is cleared by reading the receive interrupt status register (reg 0x08) 1 eof a the end of frame a bit is used to signal whether an eof event has occurred on the channel a receive. 1 = eof interrupt pending for channel a 0 = no eof interrupt pending for channel a an eof condition occurs for the channel a receiver when receive has begun and then the number of bit times specified in the serdes control register (0x06) elapse wit hout any valid bits being received. this bit is cleared by reading the receive interrupt status register (reg 0x08). 0 full a the full a bit is used to signal when the receive serdes data a register (reg 0x09) is filled with data. 1 = receive serdes data a full interrupt pending 0 = no receive serdes data a full interrupt pending a full a condition occurs when data is transferred from the channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete by te is received or when an eof event occurs whether or not a complete byte has been received. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 14 of 36 table 11. receive serdes data a addr: 0x09 reg_rx_data_a default: 0x00 76543210 data bit name description 7:0 data received data for channel a. the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. table 12. receive serdes valid a addr: 0x0a reg_rx_valid_a default: 0x00 76543210 valid bit name description 7:0 valid these bits indicate which of the bits in the receive serdes data a register (reg 0x09) are valid. a ?1? indicates that the corresponding data bit is valid for channel a. if the valid data bit is set in the receive interrupt status register (reg 0x08) all eight bits in the receive serdes data a register (reg 0x09) are valid. therefore, it is not necessary to read the receive serdes valid a register (reg 0x0a). this register is read-only. table 13. receive serdes data b addr: 0x0b reg_rx_data_b default: 0x00 76543210 data bit name description 7:0 data received data for channel b. the over-the-air received or der is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. table 14. receive serdes valid b addr: 0x0c reg_rx_valid_b default: 0x00 76543210 valid bit name description 7:0 valid these bits indicate which of the bits in the receive serdes data b register (reg 0x0b) are valid. a ?1? indicates that the corresponding data bit is valid for channel b. if the valid data bit is set in the receive interrupt status register (0x08) all eight bits in the receive serdes data b register (reg 0x0b) are valid. therefore, it is not necessary to read the receive serdes valid b register (reg 0x0c). this register is read-only. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 15 of 36 table 15. transmit serdes interrupt enable addr: 0x0d reg_tx_int_en default: 0x00 76543210 reserved underflow overflow done empty bit name description 7:4 reserved these bits are reserved and should be written with zeroes. 3 underflow the underflow bit is used to enable the interrupt a ssociated with an underflow condition associated with the transmit serdes data register (reg 0x0f) 1 = underflow interrupt enabled 0 = underflow interrupt disabled an underflow condition occurs when attempting to transm it while the transmit serdes data register (reg 0x0f) does not have any data. 2 overflow the overflow bit is used to enabled the interrupt a ssociated with an overflow condition with the transmit serdes data register (0x0f). 1 = overflow interrupt enabled 0 = overflow interrupt disabled an overflow condition occurs when attempting to write new data to the transmit serdes data register (reg 0x0f) before the preceding data has been transferred to the transmit shift register. 1 done the done bit is used to enable the interrupt that signals the end of the transmission of data. 1 = done interrupt enabled 0 = done interrupt disabled the done condition occurs when the transmit serdes data register (reg 0x0f) has transmitted all of its data and there is no more data for it to transmit. 0 empty the empty bit is used to enable the interrupt that signa ls when the transmit serdes register (reg 0x0f) is empty. 1 = empty interrupt enabled 0 = empty interrupt disabled the empty condition occurs when the transmit serdes data register (reg 0x0f) is loaded into the transmit buffer and it's safe to load the next byte [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 16 of 36 table 16. transmit serdes interrupt status [4] addr: 0x0e reg_tx_int_stat default: 0x00 76543210 reserved underflow overflow done empty bit name description 7:4 reserved these bits are reserved. this register is read-only. 3 underflow the underflow bit is used to sign al when an underflow condition associated with the transmit serdes data register (reg 0x0f) has occurred. 1 = underflow interrupt pending 0 = no underflow interrupt pending this irq will assert during an underflow condition to the transmit serdes data register (reg 0x0f). an underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the transmit serdes data register (reg 0x0f). this will only assert after the tr ansmitter has transmitted at least one bit. this bit is cleared by reading the transmit interrupt status register (reg 0x0e). 2 overflow the overflow bit is used to signal when an overflow condition associated with the transmit serdes data register (0x0f) has occurred. 1 = overflow interrupt pending 0 = no overflow interrupt pending this irq will assert during an overflow condition to the transmit serdes data register (reg 0x0f). an overflow occurs when the new data is loaded into the transmit serd es data register (reg 0x0f) before the previous data has been sent. this bit is cleared by reading th e transmit interrupt status register (reg 0x0e). 1 done the done bit is used to signal the end of a data transmission. 1 = done interrupt pending 0 = no done interrupt pending this irq will assert when the data is finished sending a byte of data and there is no more data to be sent. this will only assert after the transmitter has transmitted as least one bit. this bit is cleared by reading the transmit interrupt status register (reg 0x0e) 0 empty the empty bit is used to signal when the transmit serdes data register (reg 0x0f) has been emptied. 1 = empty interrupt pending 0 = no empty interrupt pending this irq will assert when the transmit serdes is empty. when this irq is asserted it is ok to write to the transmit serdes data register (reg 0x0f). writing the transmit serdes data register (r eg 0x0f) will clear this irq. it will be set when the data is loaded into the transmitter, and it is ok to write new data. note 4. all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imp lemented without enabling irqs. the status bits are affected by the tx enable and rx enable (reg 0x03, bits 7:6). for example, the transmit status will read 0 if the ic i s not in transmit mode. these registers are read-only. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 17 of 36 note 5. the valid bit in the transmit serdes valid register (reg 0x10) is used to mark whether the radio will send data or preamble d uring that bit time of the data byte. data is sent lsb first. the serdes will continue to send data until ther e are no more valid bits in the shifter. for example, writing 0x0f to the transmit serdes valid register (reg 0x10) will send half a byte. table 17. transmit serdes data addr: 0x0f reg_tx_data default: 0x00 76543210 data bit name description 7:0 data transmit data. the over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, foll owed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. table 18. transmit serdes valid addr: 0x10 reg_tx_valid default: 0x00 76543210 valid bit name description 7:0 valid [5] the valid bits are used to determine which of the bits in the transmit serdes data register (reg 0x0f) are valid. 1 = valid transmit bit 0 = invalid transmit bit addr: 0x18-11 reg_pn_code default: 0x1e8b6a3de0e9b222 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 address 0x18 address 0x17 address 0x16 address 0x15 table 19. pn code 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 0x14 address 0x13 address 0x12 address 0x11 bit name description 63:0 pn codes the value inside the 8 byte pn code register is used as the spreading code for dsss communication. all 8 bytes can be used together for 64 chips/bit pn code communication, or the registers can be split into two sets of 32 chips/bit pn codes and these can be used alone or with each other to accomplish faster data rates. not any 64 chips/bit value can be used as a pn code as there are certain characteristics that are needed to minimize the possibility of multiple pn c odes interfering with each other or the possibility of invalid correlation. the over-the-air order is bit 0 followed by bit 1... followed by bit 62, followed by bit 63. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 18 of 36 table 20. threshold low addr: 0x19 reg_threshold_l default: 0x08 76543210 reserved threshold low bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold low the threshold low value is used to dete rmine the number of missed chips allowed when attempting to correlate a single data bit of value ?0?. a perfect reception of a data bit of ?0? with a 64 chips/bit pn code would result in zero correlation matches, meaning the exact inverse of the pn code has been received. by setting the threshold low value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. this value along with the threshold high value determine the correlator count values for logic ?1? and logic ?0?. the threshold values used determine the sensitivity of the receiver to inter- ference and the dependability of the received data. by allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interferenc e decreases. on the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. table 21. threshold high addr: 0x1a reg_threshold_h default: 0x38 76543210 reserved threshold high bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold high the threshold high value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value ?1?. a perfect reception of a data bit of ?1? with a 64 chips/bit or a 32 chips/bit pn code would result in 64 chips/bit or 32 chips/bit correlation matches, respecti vely, meaning every bit was received perfectly. by setting the threshold high value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. this value along with the threshold low value determine the correlator count values for logic ?1? and logic ?0?. the threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. by allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to inter- ference decreases. on the other hand increasing the ma ximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. table 22. wake enable addr: 0x1c reg_wake_en default: 0x00 76543210 reserved wakeup enable bit name description 7:1 reserved these bits are reserved and should be written with zeroes. 0 wakeup enable wakeup interrupt enable. 0 = disabled 1 = enabled a wakeup event is triggered when the pd pin is deasserted and once the ic is ready to receive spi communi- cations. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 19 of 36 table 23. wake status addr: 0x1d reg_wake_stat default: 0x01 76543210 reserved wakeup status bit name description 7:1 reserved these bits are reserved. this register is read-only. 0 wakeup status wakeup status. 0 = wake interrupt not pending 1 = wake interrupt pending this irq will assert when a wakeup condition occurs. th is bit is cleared by reading the wake status register (reg 0x1d). this register is read-only. table 24. analog control addr: 0x20 reg_analog_ctl default: 0x00 76543210 reserved reg write control mid read enable reserved reserved pa output enable pa invert reset bit name description 7 reserved this bit is reserved and should be written with zero. 6 reg write control enables write access to reg 0x2e and reg 0x2f. 1 = enables write access to reg 0x2e and reg 0x2f 0 = reg 0x2e and reg 0x2f are read-only 5 mid read enable the mid read enable bit must be set to read the contents of the manufacturing id register (reg 0x3c-0x3f). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. this bit should only be set when reading the contents of the manufact uring id register (reg 0x3c-0x3f). 1 = enables read of mid registers 0 = disables read of mid registers 4:3 reserved these bits are reserved and should be written with zeroes. 2pa output enable the power amplifier output enable bit is used to enable the pactl pin for control of an external power amplifier. 1 = pa control output enabled on pactl pin 0 = pa control output disabled on pactl pin 1 pa invert the power amplifier invert bit is used to specify the polarity of the pactl signal when the paoe bit is set high. pa output enable and pa invert cannot be simultaneously changed. 1 = pactl active low 0 = pactl active high 0 reset the reset bit is used to generate a self-clearing device reset. 1 = device reset. all registers are restored to their default values. 0 = no device reset. table 25. channel addr: 0x21 reg_channel default: 0x00 76543210 reserved channel bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 channel the channel register (reg 0x21) is used to determine the synthesizer frequency. a value of 2 corresponds to a communication frequency of 2.402 ghz, while a value of 79 corresponds to a frequency of 2.479 ghz. the channels are separated from each other by 1 mhz intervals. limit application usage to channels 2?79 to adhere to fc c regulations. fcc regulations require that channels 0 and 1 and any channel greater than 79 be avoided. use of other channels may be restricted by other regulatory agencies. the application mcu must ensure that this regist er is modified before transmitting data over the air for the first time. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 20 of 36 note 6. the rssi will collect a single value each time the part is put into receive mode via control register (reg 0x03, bit 7=1). se e section for more details. table 26. receive signal strength indicator (rssi) [6] addr: 0x22 reg_rssi default: 0x00 76543210 reserved valid rssi bit name description 7:6 reserved these bits are reserv ed. this register is read-only. 5 valid the valid bit indicates whether the rssi value in bits [4:0] are valid. this register is read only. 1 = rssi value is valid 0 = rssi value is invalid 4:0 rssi the receive strength signal indicator (rssi) value indicates the strength of the received signal. this is a read only value with the higher values indicating stronger received signals meaning more reliable transmissions. table 27. pa bias addr: 0x23 reg_pa default: 0x00 76543210 reserved pa bias bit name description 7:3 reserved these bits are reserved and should be written with zeroes. 2:0 pa bias the power amplifier bias (pa bias) bits are used to se t the transmit power of the ic through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip power amplifier. the higher the register value the higher the transmit power. by changing the pa bias va lue signal strength management functions can be accom- plished. for general purpose communication a value of 7 is recommended. see table 1 for typical output power steps based on the pa bias bit settings. table 28. crystal adjust addr: 0x24 reg_crystal_adj default: 0x00 76543210 reserved clock output disable crystal adjust bit name description 7 reserved this bit is reserved and should be written with zero. 6clock output disable the clock output disable bit disables the 13-mhz clock driven on the x13out pin. 1 = no 13-mhz clock driven externally 0 = 13-mhz clock driven externally if the 13-mhz clock is driven on the x13out pin then receive sensitivity will be reduced by ?4 dbm on channels 5+13 n . by default the 13-mhz clock output pin is enabled. this pin is useful for adjusting the 13-mhz clock, but it interfere with every 13th ch annel beginning with 2.405-ghz channel. therefore, it is recommended that the 13-mhz clock output pin be disabled when not in use. 5:0 crystal adjust the crystal adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. each increment of the crystal adjust value typically adds 0.135 pf of parallel load capacitance. the total range is 8.5 pf, starting at 8.65 pf. these numbers do not include pcb parasitics, which can add an additional 1?2 pf. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 21 of 36 \ table 29. vco calibration addr: 0x26 reg_vco_cal default: 0x00 76543210 vco slope enable reserved bit name description 7:6 vco slope enable (write-only) the voltage controlled oscillator (vco) slope enable bits are used to specify the amount of variance automatically added to the vco. 11 = ?5/+5 vco adjust. the application mcu must configure this option during initialization 10 = ?2/+3 vco adjust 01 = reserved 00 = no vco adjust these bits are undefined for read operations. 5:0 reserved these bits are reserved and should be written with zeroes. table 30. reg power control addr: 0x2e reg_pwr_ctl default: 0x00 76543210 reg power control reserved bit name description 7reg power control when set, this bit disables unused circuitry and saves ra dio power. the user must set reg 0x20, bit 6 = 1 to enable writes to reg 0x2e. the application mcu must set this bit during initialization. 6:0 reserved these bits are reserved an d should be written with zeroes. table 31. carrier detect addr: 0x2f reg_carrier_detect default: 0x00 76543210 carrier detect override reserved bit name description 7 carrier detect override when set, this bit overrides carrier detect. the user must set reg 0x20, bit 6=1 to enable writes to reg 0x2f. 6:0 reserved these bits are reserved and should be written with zeroes. table 32. clock manual addr: 0x32 reg_clock_manual default: 0x00 76543210 manual clock overrides bit name description 7:0 manual clock overrides this register must be written with 0x41 after reset for correct operation [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 22 of 36 table 33. clock enable addr: 0x33 reg_clock_enable default: 0x00 76543210 manual clock enables bit name description 7:0 manual clock enables this register must be written with 0x41 after reset for correct operation table 34. synthesizer lock count addr: 0x38 reg_syn_lock_cnt default: 0x64 76543210 count bit name description 7:0 count determines the length of delay in 2-s increments fo r the synthesizer to lock when auto synthesizer is enabled via control register (0x03, bit 1=0) and not using the pll lock si gnal. the default register setting is typically sufficient. table 35. manufacturing id addr: 0x3c-3f reg_mid 313029282726252423222120191817161514131211109876543210 address 0x3f address 0x3e address 0x3d address 0x3c bit name description 31:30 address[31:30] these bits are read back as zeroes. 29:0 address[29:0] these bits are the manufacturing id (mid) for each ic. the contents of these bits cannot be read unless the mid read enable bit (bit 5) is set in the analog control register (reg 0x20). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. the mid r ead enable bit in the analog control register (reg 0x20, bit 5) should only be set when reading the contents of the manufacturing id register (reg 0x3c-0x3f). this register is read-only. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 23 of 36 table 36. pin description pin qfn name type default description analog rf 46 rfin input input rf input. modulated rf signal received. 5 rfout output n/a rf output. modulated rf signal to be transmitted. crystal / power control 38 x13 input n/a crystal input. (refer to clocking and power management on page 4). 35 x13in input n/a crystal input. (refer to clocking and power management on page 4). 26 x13out output/hi-z output system cl ock. buffered 13-mhz system clock. 33 pd input n/a power down. asserting this input (low), will put the ic in the suspend mode (x13out is 0 when pd is low). 14 reset input n/a active low reset. device reset. 34 pactl i/o input pactl. external power amplifier control. pull-down or make output. serdes bypass mode communications/interrupt 20 dio i/o input data input/output. serdes bypass mode data transmit/receive. 19 dioval i/o input data i/o valid. serdes bypass mode data transmit/receive valid. 21 irq output /hi-z output irq. interrupt and serdes bypass mode dioclk. spi communications 23 mosi input n/a master-output-slave-input data. spi data input pin. 24 miso output/hi-z hi-z master-input-slave-output data. spi data output pin. 25 sck input n/a spi input clock. spi clock. 22 ss input n/a slave select enable. spi enable. power and ground 6, 9, 16, 28, 29, 32, 41, 42, 44, 45 vcc vcc h v cc = 2.7v to 3.6v. 13 gnd gnd l ground = 0 v. 1, 2, 3, 4, 7, 8, 10, 11, 12, 15, 17, 18, 27, 30, 31, 36, 37, 39, 40, 43, 47, 48 nc n/a n/a must be tied to ground. exposed paddle gnd gnd l must be tied to ground. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 24 of 36 figure 9. cywusb6935 48 qfn ? top view cywusb6935 48 qfn v cc nc nc v cc nc nc rfout nc rfin v cc v cc nc v cc v cc nc nc nc x13 nc nc nc v cc nc nc dioval dio irq miso ss mosi reset gnd sck x13out nc v cc x13in v cc nc nc nc pactl v cc pd * e-pad bottom side cywusb6935 top view* nc nc 15 16 17 18 19 20 21 24 22 23 14 13 48 47 46 45 38 44 43 42 37 39 41 40 12 11 10 9 2 8 7 6 1 3 5 4 27 28 29 30 31 32 33 36 34 35 26 25 nc nc [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 25 of 36 absolute maximum ratings storage temperature................................. ?65 c to +150 c ambient temperature with power applied . ?55 c to +125 c supply voltage on v cc relative to vss.........?0.3 v to +3.9 v dc voltage to logic inputs [7] .................. ?0.3 v to v cc +0.3 v dc voltage applied to outputs in high-z state .......................... ?0.3 v to v cc +0.3 v static discharge voltage (digital) [8] ........................... >2000 v static discharge voltage (rf) [8] ................................... 500 v latch up current.......................................+200 ma, ?200 ma operating conditions v cc (supply voltage)........................................2.7 v to 3.6 v t a (ambient temperature under bias) ...... ?40 c to +85 c [9] t a (ambient temperature under bias) ...........0c to +70c [10] ground voltage................................................................. 0 v f osc (oscillator or crystal frequency)........................ 13 mhz dc characteristics (over the operating range) parameter description conditions min typ [12] max unit v cc supply voltage 2.7 3.0 3.6 v v oh1 output high voltage condition 1 at i oh = ?100.0 a v cc ? 0.1 v cc ?v v oh2 output high voltage condition 2 at i oh = ?2.0 ma 2.4 3.0 ? v v ol output low voltage at i ol = 2.0 ma ? 0.0 0.4 v v ih input high voltage 2.0 ? v cc [11] v v il input low voltage ?0.3 ? 0.8 v i il input leakage current 0 < v in < v cc ?1 0.26 +1 a c in pin input capacitance (except x13, x13in, rfin) ? 3.5 10 pf i sleep current consumption during power-down mode pd = low ? 0.24 15 a idle i cc current consumption without synthesizer pd = high ? 3 ? ma startup i cc icc from pd high to oscillator stable. ? 1.8 ? ma tx avg i cc average transmitter current consumption [13] ?1.4?a rx i cc (peak) current consumption during receive ? 57.7 ? ma tx i cc (peak) current consumption during transmit ? 69.1 ? ma synth settle i cc current consumption with synthesizer on, no transmit or receive ?28.7?ma notes 7. it is permissible to connect voltages above v cc to inputs through a series resistor limiting input current to 1 ma. this can?t be done during power down mode. ac timing not guaranteed. 8. human body model (hbm). 9. industrial temperature operating range. 10. commercial temperature operating range. 11. it is permissible to connect voltages above v cc to inputs through a series resistor limiting input current to 1 ma. 12. typ. values measured with v cc = 3.0v @ 25c 13. average i cc when transmitting a 10-byte packet every 15 minutes using the wirelessusb n:1 protocol. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 26 of 36 ac characteristics [14] notes 14. ac values are not guaranteed if voltages on any pin exceed v cc . 15. this stretch only applies to every 9th sck hi pulse for spi burst reads only. 16. for f osc = 13 mhz, 3.3v @ 25c. 17. sck must start low, otherwise the success of spi transactions are not guaranteed. table 37. spi interface [16] parameter description min typ max unit t sck_cyc spi clock period 476 ? ? ns t sck_hi (burst read) [15] spi clock high time 238 ? ? ns t sck_hi spi clock high time 158 ? ? ns t sck_lo spi clock low time 158 ? ? ns t dat_su spi input data setup time 10 ? ? ns t dat_hld spi input data hold time 97 [16] ??ns t dat_val spi output data valid time 77 [16] ?174 [16] ns t ss_su spi slave select setup time before first positive edge of sck [17] 250 ? ? ns t ss_hld spi slave select hold time after last negative edge of sck 80 ? ? ns figure 10. spi timing diagram figure 11. spi burst read every 9th sck hi stretch timing diagram data from mcu mosi t sck_cyc sck t sck_hi t sck_lo t dat_su t dat_hld miso ss t ss_su t ss_hld t dat_val data data s a m p l e d r i v e data from mcu data from mcu data to mcu data to mcu data to mcu miso t sck_cyc sck t sck_hi t sck_lo ss t dat_val data d r i v e data to mcu data to mcu every 8 th sck_hi every 9 th sck_hi every 10 th sck_hi t sck_hi (burst read) d r i v e d r i v e [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 27 of 36 table 38. dio interface parameter description min. typ. max. unit transmit t tx_dioval_su dioval setup time 2.1 ? ? s t tx_dio_su dio setup time 2.1 ? ? s t tx_dioval_hld dioval hold time 0 ? ? s t tx_dio_hld dio hold time 0 ? ? s t tx_irq_hi minimum irq high time ? 32 chips/bit ddr ? 8 ? s minimum irq high time ? 32 chips/bit ? 16 ? s minimum irq high time ? 64 chips/bit ? 32 ? s t tx_irq_lo minimum irq low time ? 32 chips/bit ddr ? 8 ? s minimum irq low time ? 32 chips/bit ? 16 ? s minimum irq low time ? 64 chips/bit ? 32 ? s receive t rx_dioval_vld dioval valid time ? 32 chips/bit ddr ?0.01 ? 6.1 s dioval valid time ? 32 chips/bit ?0.01 ? 8.2 s dioval valid time ? 64 chips/bit ?0.01 ? 16.1 s t rx_dio_vld dio valid time ? 32 chips/bit ddr ?0.01 ? 6.1 s dio valid time ? 32 chips/bit ?0.01 ? 8.2 s dio valid time ? 64 chips/bit ?0.01 ? 16.1 s t rx_irq_hi minimum irq high time ? 32 chips/bit ddr ? 1 ? s minimum irq high time ? 32 chips/bit ? 1 ? s minimum irq high time ? 64 chips/bit ? 1 ? s t rx_irq_lo minimum irq low time ? 32 chips/bit ddr ? 8 ? s minimum irq low time ? 32 chips/bit ? 16 ? s minimum irq low time ? 64 chips/bit ? 32 ? s figure 12. dio receive timing diagram figure 13. dio transmit timing diagram data dio/ dioval irq data t rx_irq_hi t rx_irq_lo s a m p l e t rx_dioval_vld t rx_dio_vld data s a m p l e dio/ dioval irq data data t tx_irq_hi t tx_irq_lo t tx_dio_su t tx_dioval_su t tx_dioval_hld t tx_dio_hld s a m p l e s a m p l e [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 28 of 36 radio parameters table 39. radio parameters parameter description conditions min typ max unit rf frequency range note 18 2.400 ? 2.483 ghz radio receiver (t = 25 c, v cc = 3.3v, fosc = 13.000 mhz 2 ppm, x13out off, 64 chips/bit, threshold low = 8, threshold high = 56, ber < 10 ?3 ) sensitivity ?86 ?95 ? dbm maximum received signal ?20 ?7 ? dbm rssi value for pwr in > ?40 dbm ? 28?31 ? rssi value for pwr in < ?95 dbm ? 0?10 ? receive ready [19] ?3 5 s interference performance co-channel interference rejection carrier-to-interference (c/i) c = ?60 dbm ? 6 ? db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm ? -5 ? db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ? ?33 ? db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ? ?45 ? db image [20] frequency interference, c/i image c = ?67 dbm ? ?35 ? db adjacent (1 mhz) interference to in-band image frequency, c/i image 1 mhz c = ?67 dbm ? ?41 ? db out-of-band blocking interference signal frequency 30 mhz?2399 mhz except (fo/n & fo/n1 mhz) [21] c = ?67 dbm ? ?22 ? dbm 2498 mhz?12.75 ghz, except (fo*n & fo*n1 mhz) [21] c = ?67 dbm ? ?21 ? dbm intermodulation c = ?64 dbm f = 5,10 mhz ??32 ? dbm spurious emission ?? ? 30 mhz?1 ghz ???57dbm 1 ghz?12.75 ghz except (4.8 ghz?5.0 ghz) ???54dbm 4.8 ghz?5.0 ghz ? ? ?40 [22] dbm radio transmitter (t = 25 c, v cc = 3.3v, fosc = 13.000 mhz 2 ppm) maximum rf transmit power pa = 7 ?5 ?0.4 ? dbm rf power control range ? 28.6 ? db rf power range control step size seven steps, monotonic ? 4.1 ? db frequency deviation pn code pattern 10101010 ? 270 ? khz frequency deviation pn code pattern 11110000 ? 320 ? khz zero crossing error ? 75 ? ns occupied bandwidth 100-khz resolution bandwidth, ?6 dbc 500 860 ? khz initial frequency offset ? 50 ? khz in-band spurious ?? ? second channel power ( 2 mhz) ? ?45 ?30 dbm > third channel power (> 3 mhz) ? ?52 ?40 dbm non-harmonically related spurs ?? ? 30 mhz?12.75 ghz ???54dbm harmonic spurs ?? second harmonic ???28dbm third harmonic ???25dbm fourth and greater harmonics ? ? ?42 dbm notes 18. subject to regulation. 19. max. time after receive enable and the synthes izer has settled before receiver is ready. 20. image frequency is +4 mhz from desired channel (2 mhz low if, high side injection). 21. fo = tuned frequency, n = integer. 22. antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements. [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 29 of 36 power management timing notes 23. the pd pin must be asserted at power up to ensure proper crystal startup. 24. when x13out is enabled. 25. both the polarity and the drive method of the irq pin are programmable. see page 11 for more details. figure 15 illustrates default values for the configuration register (reg 0x05, bits 1:0). 26. a wakeup event is triggered when the pd pin is deasserted. figure 15 illustrates a wakeup event configured to trigger an irq pin event via the wake enable register (reg 0x1c, bit 0=1). 27. measured with cts atxn6077a crystal. table 40. power management timing (the values below are dependent upon oscillator network component selection) [27] parameter description conditions min typ max unit t pdn_x13 time from pd deassert to x13out ? 2000 ? s t spi_rdy time from oscillator stable to start of spi transactions 1 ? ? s t pwr_rst power on to reset deasserted v cc at 2.7v 1300 ? ? s t rst minimum reset asserted pulse width 1 ? ? s t pwr_pd power on to pd deasserted [23] 1300 ? ? s t wake pd deassert to clocks running [24] ?2000? s t pd minimum pd asserted pulse width 10 ? ? s t sleep pd assert to low power mode ? 50 ? ns t wake_int pd deassert to irq [25] assert (wake interrupt) [26] ?2000? s t stable pd deassert to clock stable to within 10 ppm ? 2100 ? s t stable2 irq assert (wake interrupt) to clock stable to within 10 ppm ? 2100 ? s figure 14. power on reset/reset timing figure 15. sleep / wake timing vcc reset pd x13out t pwr_rst t pwr_pd t spi_rdy t rst t pdn_x13 s t a r t u p irq x13out t wa ke_int t wa ke t pd t sl eep pd s l e e p w a k e i r q t stable t stable2 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 30 of 36 typical operating characteristics receiver sensitivit y 2.440g hz, 3.3v -100 -98 -96 -94 -92 -90 -88 -86 -50-30-101030507090 te m p (degc) sensitivit y ( dbm ) spec m in spec typ tem p spe c typical ber sensitivity vs temp guid: 0x0ecc7e75 -98.0 -97.5 -97.0 -96.5 -96.0 -95.5 -95.0 -94.5 -94.0 -93.5 -50 0 50 100 temperature (c) ber rx sens (dbm ) 3.3 3.7 2.6 ber sensitivity vs temp @ 2.6v -96.5 -96.0 -95.5 -95.0 -94.5 -94.0 -93.5 -93.0 -92.5 -50 -30 -10 10 30 50 70 90 temperature (c) ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aad lr14 0x0dd2e9f8 ber sensitivity vs temp @ 3.3v -97.5 -97.0 -96.5 -96.0 -95.5 -95.0 -94.5 -94.0 -50-30-101030507090 temperature (c) ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aad lr14 0x0dd2e9f8 ber sensitivity vs temp @ 3.7v -98.0 -97.5 -97.0 -96.5 -96.0 -95.5 -95.0 -94.5 -50-30-101030507090 temperature (c) ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aa d lr14 0x0dd2e9f8 ber sensitivity vs vcc @ -45c -98.0 -97.5 -97.0 -96.5 -96.0 -95.5 -95.0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 v c c ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aad lr14 0x0dd2e9f8 [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 31 of 36 ber sensitivity vs vcc @ 25c -96.5 -96.0 -95.5 -95.0 -94.5 -94.0 2.52.72.93.13.33.53.73.9 v c c ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aa d lr14 0x0dd2e9f8 ber sensitivity vs vcc @ 90c -95.5 -95.0 -94.5 -94.0 -93.5 -93.0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 v c c ber rx sens ( dbm ) lr06 0x0ecc7e75 lr07 0x17d34aa d lr14 0x0dd2e9f8 ma xi mum tr a nsmi t output powe r 2. 440ghz, 3. 3v -6 -5 -4 -3 -2 -1 0 -50-30-101030507090 temp (degc) power ( dbm ) spec m in spec typ tem p spec average tx ch40 out put powe r lr18 0x17d34e2d -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 -60 -40 -20 0 20 40 60 80 100 temp (degc) power (dbm) 2.6 3.3 3.7 tx ch0 output power lr21 0xecc7e71 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -60 -40 -20 0 20 40 60 80 100 temp (degc) power (dbm) 2. 6 3. 3 3. 7 tx ch40 output power lr20 0xdd2e6a 8 -6 -5 -4 -3 -2 -1 0 -50 -30 -10 10 30 50 70 90 temp ( degc) power (dbm) 2.6 3.3 3.7 spec m in spec typ temp spec [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 32 of 36 figure 16. ac test loads and waveforms for digital pins ordering information ordering code definition 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: venin equivalent v th th rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 r2 937 r th 500 v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load part number radio package name package type operating range CYWUSB6935-48LTXI transceiver 48-pin qfn (sawn) 48-pin qfn (pb-free) industrial cywusb6935-48ltxc transceiver 48-pin qfn (sawn) 48-pin qfn (pb-free) commercial cy marketing code: wireless usb family wusb company id: cy = cypress part number 6935 48-pin sawn qfn package x = pb-free 48-ltx temperature range: commercial/industrial c/i [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 33 of 36 package diagram figure 17. 48-pin qfn 7 7 1.0 mm lt48c (sawn) 001-53698 *a [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 34 of 36 acronyms document conventions table 41. acronyms used in this document acronym description ber bit error rate cmos complementary metal oxide semiconductor crc cyclic redundancy check fec forward error correction fer frame error rate gfsk gaussian frequency-shift keying hbm human body model ism industrial, scientific, amd medical irq interrupt request mcu microcontroller unit nrz non return to zero pll phase locked loop qfn quad flat no-leads rssi received signal strength indication rf radio frequency rx receive tx transmit table 42. units of measure symbol unit of measure c degree celsius db decibels dbc decibel relative to carrier dbm decibel-milliwatt hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k kilohm mhz megahertz m megaohm a microampere s microsecond v microvolts vrms microvolts root-mean-square w microwatts ma milliampere ms millisecond mv millivolts na nanoampere ns nanosecond nv nanovolts ohm pp peak-to-peak ppm parts per million ps picosecond sps samples per second v volts [+] feedback not recommended for new designs cywusb6935 document number : 38-16008 rev. *g page 35 of 36 document history page document title: cywusb6935 wirelessusb tm lr 2.4 ghz dsss radio soc document number: 38-16008 revision ecn orig. of change submission date description of change ** 207428 tge 02/27/04 new datasheet *a 275349 ztk see ecn updated reg_data_rate (0x04), 111 - not valid changed avcc annotation to vcc removed soic package option corrected logic block diagram ? cywusb6935 , figure 7 and figure 8 updated ordering information section added ta b l e 1 internal pa output power step table corrected figure 17 caption updated radio parameters added commercial temperature operating range in section 10 updated average transmitter current consumption number *b 291015 ztk see ecn added t stable2 parameter to table 40 and figure 15 removed addr 0x01 and 0x02?unused *c 335774 tge see ecn corrected figure 7 - swap rfin / rfout corrected reg_control - bit 1 description added section 12.3 - typical operating characteristics *d 391311 tge see ecn added receive ready parameter to ta b l e 3 9 *e 2770967 dpt 09/29/09 added 48qfn package diagram (sawn) saw marketing part number in ordering information. *f 2897889 tge 03/23/10 removed inactive parts from ordering information. updated packaging information *g 3048368 hemp 10/05/2010 sunset review; no technical updates. format updates per template. [+] feedback not recommended for new designs document number : 38-16008 rev. *g revised october 05, 2010 page 36 of 36 all products and company names mentioned in this document may be the trademarks of their respective holders. cywusb6935 ? cypress semiconductor corporation, 2004-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback not recommended for new designs |
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